Community Newsletter: November 2024

IN THIS ISSUE:

• Message from the Chair
• A Year of Progress and Upcoming Opportunities
• News from Accellera Working Groups
• SystemC 3.0.1 Now Available
• Federated Simulation User Group Formed
• New Videos from our Working Groups!
• Portable Stimulus and Clock Domain Crossing
• Upcoming Events
• DVCon U.S. 2025
• DVCon China 2025
• Recent Event Wrap-up
• DVCon Taiwan
• DVCon India
• DVCon Europe
• SystemC Evolution Day
• Visit the DVCon Archives for Past Presentations, Videos and More!
• IEEE Get Program Update

 

Message from the Chair

As we approach the end of another year, I’d like to extend my warmest holiday greetings to all of you. Even with the holidays near, our dedicated volunteers and working group leaders continue their important work developing the best standards in the industry.

There is much to celebrate as we close out 2024. Many of our working groups are on track to meet important year-end milestones. The CDC Working Group is preparing for another public review, while the SystemC-AMS, SystemVerilog-MSI, and Functional Safety working groups have drafts that are coming soon. Meanwhile, the UVM-MS Working Group has successfully completed its public review and is gearing up to present version 1.0 to the Board of Directors soon. These accomplishments are in addition to the recently completed releases of PSS 3.0 and SystemC 3.0.1, as well as the considerable progress we’ve made in the Federated Simulation Standard Working Group.

But there is still much to do, and your contributions are important. Join one of our working groups, pose questions and share your insights on our public forums, or attend one of our Design and Verification Conferences (DVCons) held around the world. Over the years, DVCon has expanded and now includes six global regions. In addition to North America, we have conferences in Europe, India, China, Japan, and Taiwan. This expansion has brought even more collaboration and regional flavors to our conferences. For example, DVCon Europe hosted a SystemC Modeling Challenge, while Taiwan’s event was co-located with RISC-V Taipei Day, and India’s conference included expanded coverage into Southeast Asia.

As we prepare to close 2024, it’s impossible not to acknowledge the profound impact AI is having on our industry. Some questions for our community: What are the opportunities for Accellera in this new AI-dominated tech world? How will AI impact the future of EDA? How will AI shape the next generation of tools and methodologies? What new standards opportunities—and challenges—lie ahead for EDA as AI continues to dominate the landscape? We welcome your input as we navigate this evolving landscape.

I look forward to another year of progress, collaboration, and innovation with all of you.

Wishing you a joyful holiday season and a happy new year ahead.

Sincerely,
Lu Dai, Accellera Systems Initiative Chair

 

News from Accellera Working Groups

SystemC 3.0.1 Now Available!

The latest release of the SystemC Class Library, SystemC 3.0.1, represents a significant step forward in aligning with the IEEE 1666-2023 Language Reference Manual. This update introduces a variety of enhancements, bug fixes, and expanded platform support.

Key bug fixes and improvements include:

• Alignment with IEEE 1666-2023:
• Completed the remaining changes to match sc_bind with the revised IEEE 1666-2023 definition
• Updated the implementation of reset event notification in sc_process_b::trigger_reset_event to comply with IEEE 1666-2023
• Performance Enhancements:
• Refactored integer tracing and file writing for improved performance
• Enhanced the non-regression test suite
• Compiler and Build Improvements:
• Cleaned up various compiler warnings and improved support for sanitizers
• Addressed issues in autotools and enhanced CMake build flows
• Updated the list of supported operating systems and compilers
• Removed configurations that are no longer supported from build flows
• Datatype Management:
• Fixed various issues in datatype management, resulting in better performance

These updates ensure that SystemC 3.0.1 is more robust, efficient, and compliant with the latest standards, providing a better experience for developers and users alike.

Visit the SystemC Community Portal for the latest updates and information regarding SystemC.

Federated Simulation User Group Formed: A New Frontier for Accellera

By Mark Burton, Federated Simulation Standard Working Group Vice Chair

Historically, Accellera has concentrated on developing languages and creating simulation environments tailored to specific applications. However, with critical communication and interoperability between simulation environments becoming necessary, as well as between standards organizations themselves, Accellera has formed the Federated Simulation Users Group (FSUG). This new initiative is a significant advancement toward creating a cohesive simulation ecosystem that can adapt to increasingly complex demands in both hardware and software.

The Federated Simulation Initiative
To bring this vision to life, Accellera introduced the Federated Simulation Working Group earlier this year, tasked with formalizing the standards necessary for efficient cross-communication between simulation environments. This working group is complemented by the Federated Simulation User Group, a community-driven body designed to guide the development of the standard and foster collaborations with other standards organizations. By offering an open structure that includes both Accellera members and non-members, and meeting as frequently as the working group, FSUG encourages a truly federated approach to standardization.

This dual structure of the working and user groups serves a dual purpose. On one hand, it provides a pathway for organizations to join Accellera and contribute to the evolving standard. On the other hand, it creates a technical space for developers and engineers to tackle real-world challenges within this federated ecosystem. In essence, this new approach is designed to align technical solutions with organizational needs, allowing users and stakeholders to collaborate on resolving issues that affect multiple domains and industries.

Defining the Direction of Federated Simulation
Although the Federated Simulation Initiative is still in its early stages, some key directions have already been outlined. For instance, the scope will cover enabling data to be injected/extracted from Virtio interfaces directly into a software stack, as much as connections to GPIO hardware interfaces, enabling hardware in the loop as much as software in the loop.

This direction underscores a major goal of the initiative: to consolidate existing mechanisms into a unified structure. While individually these techniques are well-established, the Federated Simulation Initiative aims to bring them together within a shared ecosystem.

Tackling Synchronization and Domain-Specific Challenges
One of the core challenges the working group faces lies in managing synchronization across diverse simulation environments. Different domains often employ unique synchronization protocols that may not be compatible with one another. While the actual data being transmitted is typically domain-specific, the synchronization mechanisms must be adaptable to various simulation or execution environments. To address this, the working group will invest significant effort into finding and standardizing synchronization strategies that can work seamlessly across different systems.

Looking Ahead: The Role of the Federated Simulation User Group
The Federated Simulation User Group is central to the initiative’s mission. By encouraging open participation and frequent meetings, the FSUG invites insights from a broad community of engineers, developers, and organizations to enrich the standard with real-world experience. Its role in guiding the standard ensures that the direction of federated simulation aligns with the needs of its users, both today and in the future.

As the Federated Simulation Initiative continues to evolve, it holds the potential to redefine how simulation environments work together, allowing for efficient communication across software and hardware boundaries. This vision of unified simulation could streamline the workflows of many industries, setting the stage for future innovations that transcend individual domains and bring standards organizations together in unprecedented ways.

You can find more information on the user group and how to get involved on the Federated Simulation Standard Working Group page.

 

Latest Videos from our Working Groups

Portable Stimulus

Members of the Portable Stimulus Working Group presented a tutorial titled “Efficient Portable Programming-Sequence Development with PSS” during DVCon U.S. 2024. The tutorial is divided into sections that include what Portable Stimulus is, the motivation behind the Portable Test and Stimulus Standard (PSS), developing reusable test content at the block level, sub-system and SoC-level testing with PSS, and post-silicon testing with PSS.

For more information and resources on Portable Stimulus, or to download the Portable Test and Stimulus Standard 3.0, visit the Portable Stimulus Working Group page.

Clock Domain Crossing

Clock Domain Crossing (CDC) Working Group members presented a workshop during DVCon U.S. 2024, “Hierarchical CDC & RDC Closure with Standard Abstract Models.” A hierarchical verification approach is becoming necessary as complexity and the number of clock domains increase in ASIC designs. The workshop covered basic CDC and Reset Domain Crossing (RDC) knowledge, CDC Setup and Constraints, Structural CDC/RDC, Hierarchical CDC/RDC, and CDC Assertions.

For more information and the latest updates from the working group, visit the Clock Domain Crossing Working Group page.

 

Upcoming Events

Mark Your Calendar for DVCon U.S. 2025!

The 37th annual DVCon U.S. will be held February 24-27, 2025, at the Doubletree Hotel in San Jose, California. Advance registration is open, and the program will be published soon. For the latest updates and to register, visit the DVCon U.S. 2025 website.

For inspiration, the proceedings from DVCon U.S. 2024 are available to view on demand.

DVCon China 2025

DVCon China will be held April 16, 2025 at the Shanghai Renaissance Pudong Hotel in Shanghai, China. The call for abstracts is open through December 23, 2024. For the latest updates on the conference, including exhibitor and registration information, visit dvcon-china.org.

Dear attendees and colleagues,
Welcome to the 2025 DVCon China Conference! As the chair of this conference, l am truly honored to be here with all of you. lt's exciting to gather together and discuss the latest trends and cutting-edge technologies in the field of design verification.

In recent years, we've seen tremendous growth in China's chip development across various sectors, particularly in critical areas like CPUs, GPUs, artificial intelligence, automotive electronics, communications, and the Internet of Things (loT). lt's inspiring to witness the rapid rise of domestic companies in these fields, which not only drives technological advancement but also enhances our overall market competitiveness.

As we continue to accelerate chip development, our community of design verification engineers is expanding at an impressive pace. More talented engineers are joining our ranks, bringing fresh perspectives and innovations that are vital to our industry's progress. Design verification is not just about ensuring product quality; it’s also key to improving our overall research and development efficiency.

While we strive for speed and efficiency, we must also emphasize creativity and innovation. Whether it’s through developing new tools and processes or creatively solving challenges in our engineering projects, the contributions of design verification engineers are crucial. lt's through our commitment to continuous innovation that we can stay competitive in this fast-paced market.

Every year, the DVCon China Conference attracts hundreds of engineers from leading companies across the country. This gathering is not only about learning and sharing knowledge, but it's also a fantastic opportunity to connect and network with fellow professionals. l encourage you to take advantage of this platform to explore the latest features of lC tools, discover new solutions, and make new friends in the industry. l hope you leave this conference with valuable insights that will benefit you both technically and personally.

Thank you all for being here, and l look forward to an enriching and exciting conference experience together!

Thank you!
Bin Liu, DVCon China 2025 General Chair

More Upcoming Events

For more information on Accellera events planned throughout 2025, visit the Accellera Events page.

 

Recent Event Wrap-up

DVCon Taiwan 2024

DVCon Taiwan 2024, co-located with RISC-V Taipei Day, was an enormous success. The two-day event in September attracted over 200 registered attendees, who participated in 21 technical presentations, 10 exhibit booths, three keynote sessions, and one interactive panel. Alessandra Nardi, Chair of Accellera’s Functional Safety Working Group, presented a keynote, “May the Dependability Be with You: Reliability and Resilience Challenges in SoC Design.” For more event insights and photos, visit the DVCon Taiwan LinkedIn page.

Looking ahead, DVCon Taiwan 2025 is set for September 9. Check the DVCon Taiwan website for the latest updates.

DVCon India 2024

DVCon India, held in September in Bangalore, enjoyed participation from nearly 1,300 attendees and exhibitors over the two-day event.

A reception was held to honor those with significant contributions to the advancement of technology in India. Dr. Satya Gupta received the Lifetime Achievement Award; Samsung Semiconductor India Research received the company award for Exemplary Contribution in Design and Verification; Outstanding Contribution in Design and Verification for an Individual was awarded to Prakash Easwaran; the Woman Achiever in the Semiconductor Industry was presented to Dr. Srobona Mitra; and Vellore Institute of Technology, Vellore won the award for Best Educational Institution.

A virtual Design Contest was held ahead of the conference titled, “C-DAC’s VEGA microprocessor (RISC-V) based Design & Verification Challenge” inviting all academic students to participate. The winning team “BitWeavers” included Kuruppumullage Don Supun Dasantha Kuruppu, Dakshina Tharindu, and Anuki Chamathka Pasqual from the University of Moratuwa, Sri Lanka.

The award for Best Paper went to Dipanshu, Mukesh Gandhi, Arnab Ghosh, and Parag S Lonkar of Samsung for their paper, “A Generic Clock UVC for Generating and Testing of High Speed PLL and CDR.”

Best Poster honors went to Nikhil Singla, Pandithurai Sangaiyah, and Rohit Jindal of Google for their poster, “ML-Based Regression Accelerator.”

Save the Date! DVCon India 2025 will be held September 10-11, 2025. Stay up to date by visiting the DVCon India 2025 website.

DVCon Europe 2024

DVCon Europe 2024, held last month at the Holiday Inn Munich City Centre in Munich, Germany, was a tremendous success attracting over 350 attendees. The format of DVCon Europe remains unchanged. This year it began with 16 in-depth tutorials on day one, followed by 20 technical paper presentations on day two, including several academic research papers. The event also featured 12 exhibitors showcasing their latest innovations and solutions.

The Best Paper Award in the engineering category went to Vishal Chovatiya, Gabriel Rutsch, and Wolfgang Ecker of Infineon Technologies for “Addressing Fixed-Point Format Issues in FPGA Prototyping with an Open-Source Framework.” Francesco E Brambilla, Davide Ceresa, Jashandeep Dhaliwa, Stefano Esposito, and Kostas Kloukinas of CERN, and Jeffrey Prinzie of KU Leuven, picked up Best Research Paper for “Virtual Prototyping Framework for Pixel Detector Electronics in High Energy Physics.”

“Formal RTL Sign-off with Abstract Models,” received the Best Presentation Award (voted for by conference attendees). The authors were Lucas Deutschmann (RPTU Kaiserslautern-Landau), Osama Ayoub and Tobias Ludwig (LUBIS EDA), Wolfgang Kunz (Infineon Technologies), and Rohith Batthineni, Michael Schwartz, and Dominic Stoffel. 

For a more detailed summary of DVCon Europe 2024, check out Jakob Engblom’s blog post, “Notes from DVCon Europe 2024,” on SemiWiki.com. Jakob was Vice Chair of DVCon Europe 2024.

Next year’s DVCon Europe will be held October 14-15, 2025. For more information, visit the DVCon Europe website.

SystemC Evolution Day 2024

SystemC Evolution Day is co-located with DVCon Europe each year and held the day after the conference and exhibition in Munich. Participants shared insights and explored new ideas for advancing SystemC standards, with a strong emphasis on thread safety and enhancing interoperability with other simulation environments. Accellera’s latest initiative in Federated Simulation was also highlighted as a potential area for future synergy within the SystemC ecosystem. For more details on SystemC Evolution Day, including past presentations, visit the SystemC Events page in the SystemC Community Portal.

DVCon Archives

For proceeding from past DVCon conferences around the globe, visit the DVCon archive site.

 

IEEE Get Program Update

Since its inception, the Accellera-sponsored IEEE Get Program has resulted in over 199,500 downloads. The IEEE Get Program provides no cost access of electronic design and verification standards to engineers and chip designers worldwide. For more information and to view the standards available for download, visit the Available IEC/IEEE Standards page on the Accellera website.

 

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